1. Field of the Invention
The present invention relates to a semiconductor device in which trenches are formed in a semiconductor substrate and an insulator is buried in the trenches so that an element isolation region is formed and a method of fabricating such a semiconductor device.
2. Description of the Related Art
The semiconductor device of the above-described type includes non-volatile memories such as flash memories. In the non-volatile memories, an etching process requires high precision in a step of forming an element isolation region in a memory cell forming area. However, a conventional fabricating step involves factors which cannot improve the precision in the following points. FIGS. 6A to 6E illustrate typical sectional structures of a semiconductor device according to a conventional fabricating method. In FIG. 6A, firstly, a silicon oxide film 2 is formed on a silicon substrate 1. Subsequently, a polycrystalline silicon film 3 doped with phosphor (P) and a silicon nitride film 4 are formed on the silicon oxide film 2 in turn. Next, a photoresist is formed by a photolithography process into a predetermined pattern, whereby a mask is formed. The silicon nitride film 4 is etched by a reactive ion etching (RIE). The polycrystalline silicon film 4 is then etched with the silicon nitride film 4 serving as a mask so that the silicon oxide film 2 is exposed. This state is shown in FIG. 6A.
Subsequently, the silicon oxide film 2 and the silicon substrate 1 are etched so that a trench is formed in the silicon substrate. A silicon oxide film 5 is formed on the inner surface of the trench. Consecutively, a silicon oxide film 6 is deposited in the trench by a high density plasma (HDP) process. The silicon oxide film 6 is polished by a chemical mechanical polish (CMIP) process thereby to be planarized. Thereafter, the structure is heated in an atmosphere of nitrogen so as to be formed into the state as shown in FIG. 6B.
In the aforementioned state, wet etching is carried out for the silicon oxide film 6 using a solution of buffered hydrofluoric acid (BHF). The etching is carried out until a predetermined height or level is achieved on the basis of a surface of the silicon substrate 1. Consequently, an upper surface of the silicon oxide film 6 is located in the middle of the polycrystalline silicon film 3. This state is shown in FIG. 6C. Since the foregoing is the wet etching process, the silicon oxide film 5 is etched as well as the silicon oxide film 6. Accordingly, part of the polycrystalline silicon film 3 is exposed as shown in FIG. 6C.
Subsequently, the silicon nitride film 4 is etched by phosphating thereby to be eliminated. As a result, the structure as shown in FIG. 6D is obtained. Consecutively, an ONO film 7, a polycrystalline silicon film 8 doped with phosphor, a tungsten silicide (WSi) film 9 and a silicon nitride film 10 are sequentially deposited on one another so that the structure as shown in FIG. 6E is obtained. The ONO film 7 is a three-layer film composed of a silicon oxide film, silicon nitride film and silicon oxide film.
Thereafter, the silicon nitride film 10 is etched by the RIE process. The WSi film 9, polycrystalline silicon film 8, ONO film 7 and polycrystalline silicon film 3 are etched by the RIE process with the etched silicon nitride film 10 serving as a mask. A silicon oxide film is then formed on a side wall of the gate electrode. Thus, a flash memory is made through the foregoing steps.
For example, JP-A-2002-033476 and JP-A-2002-124563 each disclose a technique of STI which is an element isolation region formed by burying, with the silicon oxide film, the relatively shallow trench formed in the silicon substrate.
However, the foregoing conventional techniques have the following defects. More specifically, the silicon nitride film 4 serving as a stopper film for CMP cannot be polished uniformly when the upper surface of the silicon oxide film 6 is flattened. As a result, when the silicon oxide film 6 is etched by the solution of BHF, an amount of etching is difficult to control, whereupon the height from the surface of the silicon substrate 1 becomes non-uniform.
The non-uniform height from the surface of the silicon substrate 1 results in variations in a coupling ratio of the silicon substrate to a gate electrode which will be formed later. This results in an increase in the write time in the characteristic of the device, which increase is undesirable in the practical use.